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78M6610+PSU Data Sheet
Write Operations
Following the START (S) condition from the master, the device address (7-bits) and the R/W bit (logic low
for write) are clocked onto the bus by the master. This indicates to the addressed slave receiver that the
register address will follow after it has generated an acknowledge bit (A) during the ninth clock cycle.
Therefore, the next byte transmitted by the master is the register address and will be written into the
address pointer of the 78M6610+PSU. After receiving another acknowledge (A) signal from the
78M6610+PSU the master device will transmit the data byte(s) to be written into the addressed memory
location. The data transfer ends when the master generates a stop (P) condition. This initiates the internal
write cycle. The example in Figure 20 shows a 3-byte data write (24-bit register write).
S
Device Address
0
Register Address
Data
Data
Data
P
Figure 20: I C Bus 3-byte Data Write
S
T
A
R
T
0 1 2 3 4
5 6
A
C
K
0
1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
2
A A
C C
K K
A
C
K
0 1 2 3 4 5 6 7
A S
C T
K O
P
Upon receiving a STOP (P) condition, the internal register address pointer will be incremented.
The write access can be extended to multiple sequential registers. Figure 21 shows a transaction where
multiple register are written sequentially.
REGISTER (n)
REGISTER (n+1)
REGISTER (n+2)
REGISTER (n+x)
S
Device Address
0
Register Address (n)
Data
Data
Data
P
S
T
A
R
T
0 1 2 3 4
5 6
A
C
K
0
1 2 3 4 5 6 7
A
C
K
0 1 2 3 4 5 6 7
A
C
K
0 1 2 3 4 5 6 7
A
C
K
0 1 2 3 4 5 6 7
A
C
K
0 1 2 3 4
6 7
A
C
K
0 1 2 3 4
6 7
A
C
K
Figure 21: I C Bus Multiple Sequential Register Write
2
Read Operations
Read operations are initiated in the same way as write operations with the exception that the R/W bit of
the control byte is set to one. There are two basic types of read operations: current address read and
random read.
Current Address Read: the 78M6610+PSU contains an address counter that maintains the address of the
last register accessed, internally incremented by one when the stop bit is received. Therefore, if the
previous read access was to register address n, the next current address read operation would access
data from address n + 1.
Upon receipt of the control byte with R/W bit set to one, the 78M6610+PSU issues an acknowledge (A)
and transmits the eight bit data byte. The master will not acknowledge the transfer, but generates a STOP
condition to end the transfer and the 78M6610+PSU will discontinue the transmission.
S
Device Address
1
Data
Data
Data
P
S
T
A
R
T
0 1 2 3 4
5 6
A
C
K
0 1 2 3 4 5 6 7
A
C
K
0 1 2 3 4 5 6 7
A
C
K
0 1 2 3 4 5 6 7
N S
O T
O
A P
C
K
This read operation is not limited to 3 bytes but can be extended until the register address pointer
reaches its maximum value.
Rev 1
51
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